Production Programming of Flash for FPGAs and MCUs...

This's from comp.arch.fpga-Google group ...

Experience/thoughts or answers of the members of the group  ..... 

1.

Someone on Linkedin asked about a stand alone device for programming 

the flash for FPGAs in the field or in a production environment. 

There doesn't seem to be anything currently available like this. 

Looking at the big three manufacturers I see at least two formats for 

the files that might be used.  Xilinx and Lattice use SVF with Xilins 

offering support for a compressed version called... XSVF of course. 

Altera uses JAM.  JAM seems to be a JEDEC standard while SVF appears 

to be a defacto industry standard developed by a company. 

I'm curious why two standards came about.  Was there a problem with 

using the version the company developed?  I'm assuming the industry 

version came first and the JEDEC version came later.  Or is that 

wrong?  It won't be too much trouble to support both, but I don't get 

why both standards exist. 

How do you program production devices?  I know in large facilities 

they pay big bucks for JTAG hardware and software that will work 

across the spectrum including test and diagnosis.  I'm thinking there 

is a market for a more limited device that is just used to program the 

non-volatile memory in embedded systems in an efficient manner for 

production and field upgrades.  Any thoughts? 

2.

Programming procedure for programming a bare at91sam9 board. 

1. Insert SD-Card 

2. Press reset 

3. Wait until LED blinks 

4. Remove SD-Card 

5. Press Reset 

    Application boots... 

Procedure for updating the linux kernel in a preprogrammed board. 

1. Connect board to host PC using USB. 

2. Reset the board in the USB Mass Storage mode. 

3. Wait until FAT partition window appears on the host PC. 

4. Clíck on the new kernel version, drag and drop it on the FAT window 

5. Reset the PC into normal linux boot sequence. 

 

3.

I know where I've been we always ended up building our own board with 

MCU on 

it for the production testing. Usually involving bit- 

banging(everything from JTAG to PCI) 

a bootloader or test program into the dut and programming a flash via 

uart/spi or 

something like that 

the code to be programmed was usually store on flash on the board, so 

unless you 

needed to add serial numbers and such it could be used standalone, 

just plug it into 

the dut and push the program button and done 

We did at one point try some jtag hw, but it could never really do 

what we wanted 

4.

IEEE 1532 is something that is a bit newer, I believe both xilinx and 

altera 

support it, not sure 'bout the others. http://grouper.ieee.org/groups/1532/ 

(we are primarily Xilinx users...) 

As for programming, it depends on the system.  These days we usually 

have a PC in the test fixture for all but the simplest of boards, so 

we use 

a Xilinx cable for the initial load.  We usually have the Xilinx part 

as a coprocessor 

with other devices, so even if the xilinx boots first, we have other 

devices that 

can do updates to the memory already on-board. 

Even if you don't have a CPU, it's not hard to put in a picoblaze core 

and do a 

loader to update a SPI flash via bit-banging.  You could probably do 

one with 

access to raw SD/MMC cards without too much trouble. 

5.

It depends on the devices in question. 

Many larger microcontrollers have a bootloader in ROM that you can use 

to program them over a serial link or perhaps USB.  Smaller 

microcontrollers can often be programmed easily using a JTAG or other 

debugging port, or an SPI-like interface (such as AVR devices). 

Typically that means using the manufacturer's own JTAG debuggers and 

software, but these are always far cheaper than the JTAG test equipment 

and software you describe. 

I have also used the JTAG or BDM port of bigger microcontrollers, 

combined with a cheap hardware interface and gdb, to script programming 

and testing setups.  For ARM devices you can use OpenOCD or Urjtag in a 

similar fashion. 

For devices that can boot from a serial flash, the easiest method is 

often to make these pins available on a header, along with the "boot 

mode" control pins for the device.  Then you can make a little card with 

a serial flash device that you plug into the board for initial bootup - 

this software can then test the board and program the real code into the 

main memory. 

If you have a serial flash on the board as the main memory, then you can 

have a similar header that lets an off-board device hold the processor 

or FPGA in reset while it programs the serial flash.  You can make such 

a device using an FTDI 2232H module and a few wires. 

6.

I try to stick with devices which can be programmed over a standard 

serial port. A programmer is nothing more than a USB to serial 

converter. Very convenient. 

If I need in system programming I use a standard programmer with a 

cable. IC socket to put in the programmer at one end, a special 

connector on the other end. 

In order to program large numbers of devices I once build a special 

rig with 8 Jtag and 8 serial ports. The devices to be programmed where 

designed to be plugged into this programmer. There is a lot you can do 

at the design stage to make programming easier & faster. A cheap 

device may cost more in the end if the programming takes more time & 

effort. Time is expensive in many places. 

RSRTC Recruitment 2011 Admit Card

RSRTC Recruitment 2011 Admit Card

The written exam tentative date is 18/12/2011 instead of 27/11/2011.For more detail please see here:

source:http://www.rsrtc.gov.in/Vacancy.asp

http://www.rsrtc.gov.in/

Note: - 1. The ad described the expected date of written test for recruitment to posts dated 18 / 12 / 2011 is certainly one of | the test of time will be 2 hours, which is 11: 00 am-1: 00 pm will be |              2. Corporation as per the syllabus of multiple choice questions paper published on the website | Paper of the two sections will total 80 points | including 40 points and 40 points in question will be common knowledge to all matters related to the question paper will have questions | Advertising described in the final 20 points of merit formula that calculated Javegi |              3. question papers for the North will not be a negative mark |              4. would not be interviewing for the posts | Only selected on the basis of merit formula Javega | RSRTC Employees Service Regulations 1965, revised rules and Recruitment / Promotion schedule under the provisions described in the eligibility for the various post for eligible candidates.

Syllabus (PART-A + PART-B)
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Last Updation: 16/11/2011

JNTU Hyderabad PTPG Notification 2011-Part Time Admissions in M.Tech, M.Pharm, MSc, MBA

JNTU Hyderabad PTPG Notification 2011-Part Time Admissions in M.Tech, M.Pharm, MSc, MBA

Jawaharlal Nehru Technological University, Hyderabad (JNTUH) has announced notification for admission to Part Time Post Graduate Programs(PTPG) in M.Tech., M.Sc., MBA and M. Pharmacy for the year 2011-12. The Part - Time Programs are offered in Engineering / Sciences/ Pharmacy/ Management disciplines. These pro...grams are best suitable for those like to upgrade their educational qualification while working. You can pursue these courses without leaving your job. The Part - Time programs are offered for the candidates who have been employed in and around Hyderabad. Following are details of programs, eligibility and application procedure:

Details of Part Time Programs of JNTU- H:

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Application Procedure: Candidates can obtain application format from JNTUH website mentioned above. Test Syllabus for written exam, Eligibility Criteria and other details also available on website. Application fee is Rs. 1000. Address: Jawaharlal Nehru Technological University, Kukatpally, Hyderabad - 500085, Andhra Pradesh, India. Phones : +91-040-23158661 to 23158664.

Important Dates:

1. Last date for submission of applications: 25-04-2011
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Osmania University B.Ed 3rd Methodology Admissions 2012

Osmania University B.Ed 3rd Methodology Admissions 2012

Osmania University has announced notification for admission into B.Ed 3rd Methodology - 2012 programme. The office of the Center for B.Ed and M.Ed (Distance Mode), Institute of Advanced Studies in Education (IASE), Osmania University is inviting applications from the in-service teachers working in Andhra Pradesh. They should have also passed in B.Ed degree from any recognised university.

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Important Dates:

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Coding Style of Verilog HDL-Modules

Verilog is a one of the famous Hardware Descriptive Languages (HDL). (VHDL is the other one). Verilog langauage syntax very well matches with C language syntax. This is big advantage in learning Verilog. Logic operators, data types, loops are similar to C. In addition to this certain data types which are necessary to describe a hardware are available in Verilog. For example, nets in a schematic or hardware design is refered here as 'wire'. Flip-flops (or in general are called as registers) are defined as type 'reg'.

"module"s are building block of Verilog. Consider any design represented by a block diagram with its inputs and outputs.

Consider a design named "A". Let "Input1" and "Input2" are its inputs. Let "output1" be its output. In verilog we define this design "A" as module "A" and its inputs and outputs become Input/Output (I/O) "ports" of that module. The keyword for declaring the module in Verilog is "module". This keyword should be followed by the name of the module, in this case it is "A". Hence it becomes :module A. Thus complete syntax of declaring or defining a hardware circuit is as follows:


module ();

            input ---- ; // telll which are inputs

            output ---- ; //these are outputs

             ------------------------------

             ------------------------------

           

            --------------------------------

endmodule

Where,

module ==> Verilog keyword to declare a name of the hardware circuit.

 ==> Name of the module i.e. hardware circuit. (Here it is "A").

 ==>  'terminal' is Verilog way of naming I/O ports, here we should specify all inputs and outputs of circuit. Outputs are written first. Why? Answer is "That's how Verilog is !!!!"

input ==> Verilog keyword to tell the Verilog compiler which are inputs of the module in the given list of .

output ==> Verilog keyword to tell the Verilog compiler which are outputs of the module in the given list of .

endmodule ==> Another verilog keyword to tell that module related all definitions are over and this is the end of the module.

; ==> This semi colon represents end of line.

// --> represents start of comment; same as C syntax.

( /*……………………………..*/  are multiple line comment)



So above design "A" can be defined in Verilog as given below:

module A (Output1, Input1, Input2)

                   output Output1;

                   input Input1, Input2;

                    -------------

                    -------------

 endmodule



If above design is a T flip-flop then we can write module description as:



module T_FF(q,clock,reset); // Here q is o/p; must be first

                    //Other control i/pts must be next i.e. clk and reset inputs]

                    -------------

                    --------------

                   

endmodule

Nesting of modules is not allowed in verilog. One module definition can't contain another module definition within the 'module ' and 'endmodule' statements.

Hardware circuit of design "A" can be defined in 3 different ways in Verilog. They are:

1. Gate level modeling

2. Data flow modeling

3. Behavioural modeling

MBA after BBA- Good or bad

MBA after BBA- Good or bad

source:http://www.apcollegeadmissions.com

It is good to note that you are pursuing BBA with specialization in Finance. The students of Bachelors in Business Administration (BBA) learn organizational skills, management concepts and business discipline. BBA students develop competencies in organizational skill, help to enlarge the management, by their decision-making styles, and handle the management well through their skilled and well organized planning and execution. Hence employability opportunities are good with a BBA degree. 

The option of pursuing higher studies in management i.e. MBA or to seek employment depend on your aptitude, career objective and economic needs. Candidates who have finished their education in BBA can get employed as management trainee or as an executive trainee in any of the reputed companies or MNCs. Sectors such as Banking, Finance, Consultancy, Consumer Durable Companies, FMCG, IT Companies, Advertising Agencies and many more are employing BBA graduates with attractive pay packages to meet their executive talent requirements. The salary ranges from Rs.1.50 lakh upwards and is dependent on your merit and how well you perform in your recruitment process. If you seek placement, you must develop well in your soft skills and communication skills before you graduate. This will provide you an edge over others.

As MBA is the most ideal course after BBA, if you wish to pursue higher education. If you opt for higher education it is suggested that you qualify in any one of the common admission tests like Management Aptitude Test (MAT), Common Aptitude Test (CAT), Xavier Aptitude Test (XAT) etc. which will fetch you a seat in top B-Schools. It would be a good idea to work for a couple of years in a reputed corporate after your BBA degree, gain valuable experience in organizational functioning and then pursue MBA from a top B-School. However, this requires high focus and determination.

ASIC design job vs FPGA design job Options

ASIC design job vs FPGA design 

 THIS IS FROM  comp.arch.fpga group ...... 

question:

I am an ASIC design engineer with over 6 years experience. My experience 
 in ASIC design spans across microarchitecture, RTL coding, synthesis, 
 timing closure and verification. Is it advisable for me if I change to a 
 FPGA design job? I mean, what are the pros and cons? I do not have much 
experience in FPGA other than school projects. How much learning is 
 involved? Will it be difficult to switch back to ASIC design position in 
 the future if I move to a FPGA job? Do FPGA design involve less work and 
 stress than ASIC? Please provide your opinion, experience or any other 
 comment. 

 answer by anonymous author  : I knew a guy who had done really good FPGA designs for years, and for 
years had yearned to do ASIC design with the "big boys".  He lasted a 
year or two -- not because he wasn't up to the job, but because he hadn't 
realized the difference in the design cycle between ASIC and FPGA, and he 
vastly preferred FPGA design. 

Because with FPGA design, you do your system design and have a design 
review, then you do your coding and have a design review, and then you 
pour it all into the PC board that's been underway at the same time that 
you were doing your FPGA design.  You bring it all up with the test 
features in the software whose design has _also_ been underway while you 
were working, and you test the heck out of it. 

At this point, you're far from done: the board will be getting green 
wires, the software will be getting revised (or, if everyone is smart, 
only the critical portions of the software will have been completed), and 
your logic design will probably need revision (or be incomplete). 

So it's not uncommon to spend a month or two tweaking and revising your 
"finished" design after it's finished. 

Tom's experience with ASIC design, on the other hand, was that you get 
the system design done, then you go write a bunch of behavioral code to 
completely embody the system design, and a testbench to completely test 
it.  You churn on that for weeks or months while your colleagues make up 
new tests for corner cases.   

Then, once you've verified the snot out of the system design, you start 
replacing parts of your behavioral system piece-by-piece with the RTL- 
level code for your ASIC, testing all the way. 

So, (in Tom's words), you spend 90% of your time flogging the 
verification. 

This all makes sense:  the cycle time between moving a comma in a Verilog 
file and testing the effect in an FPGA might only take between half an 
hour and several hours.  The cycle time to do the same thing with an ASIC 
is weeks, and $$$, and trash bins full of parts.  So doing the 
verification "live" makes good economic sense with FPGAs, and doing it in 
simulation makes equally good economic sense with ASICs. 

So:  if the design cycle that I'm quoting for ASICs sounds accurate to 
you (I'm just forwarding a long-ago conversation), and the design cycle 
for FPGA work makes you think "ewww!", then FPGA work isn't for you.  If, 
on the other hand, you get no joy from spending 90% of your time 
verifying before you actually get to see your work working -- maybe 
you'll like FPGA work. 

Tom did note barriers to transitioning to ASIC work (in part because he 
has an EET degree, not a "real" EE degree), and may not have found the 
transition back to FPGA work as easy as he did if he did not have a large 
circle of former coworkers who -- to a man -- were impressed by his work 
and willing to tell their bosses.  (Tom's one of those guys that if he's 
applying for work you tell your boss "just hire him, he'll make it work"). 

So, that's what I know.