lab

1. A VHDL PROGRAM FOR AN N-BIT AND GATE USING GENERIC STATEMENT IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.Std_logic_1164.all;

entity nbitand is

              generic ( n: integer:=8 );

              port( a,b: IN              STD_LOGIC_VECTOR(n-1 DOWNTO 0);

                  and_out: out STD_LOGIC_VECTOR(n-1 DOWNTO 0));

end nbitand; 

architecture arch of nbitand is

signal i: integer;

begin

              process(a,b,i)

              begin

              for i in 0 to n-1 loop

                            and_out(i) <= a(i) and b(i);

              end loop;

end process;

end arch;

 

 

 

 

 

 

 

SIMULATION RESULTS:

 

2. A VHDL PROGRAM FOR HALF ADDER IN DATAFLOW MODEL

Library ieee;

Use ieee.std_logic_1164.all;

entity halfadder is             

              port(a,b: in std_logic;

              sum,ca:out std_logic);

end halfadder;

architecture halfadder of halfadder is

begin

              sum <= a xor b;

              ca <= a and b;

end halfadder;

 

SIMULATION RESULTS:

 

3. A VHDL PROGRAM FOR FULL ADDER USING TWO HALF ADDERS IN STRUCTURAL MODEL

Library ieee;

Use ieee.std_logic_1164.all;

entity fulladder_h is

              port(p: in STD_LOGIC;

                            q: in STD_LOGIC;

                            cin: in STD_LOGIC;

                            s: out STD_LOGIC;

                            carry_out: out STD_LOGIC);

end fulladder_h;

architecture fulladder_h of fulladder_h is

component halfadder

              port(a,b:in std_logic;

              sum,ca:out std_logic);

end component;

component or11

              port(d1,d2: in std_logic;

              q:out std_logic);

end component;

signal si,ci,yi: std_logic;

begin

f1: halfadder port map(p,q,si,ci);

f2: halfadder port map(si,cin,s,yi);

f3: or11 port map(yi,ci,carry_out);

end fulladder_h;

 

 

 

 

 

SIMULATION RESULTS:

 

4. A VHDL PROGRAM FOR FULL ADDER IN DATA FLOW MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity fa is

              port (              p: in STD_LOGIC;

                            q: in STD_LOGIC;

                            c: in STD_LOGIC;

                            s: out STD_LOGIC;

                            carry: out STD_LOGIC);

end fa;

architecture arch of fa is

begin

  s <= p xor q xor c;

  carry <= (p and q) or (q and c) or (c and p);

end arch;

 

SIMULATION RESULTS:

 

5. A VHDL PROGRAM FOR 4-BIT PARALLEL ADDER/RIPPLE ADDER IN STRUCTURAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity parallel_4 is

              port (              a: in STD_LOGIC_VECTOR (3 downto 0);

                            cin: in STD_LOGIC;

                            sum: out STD_LOGIC_VECTOR (3 downto 0);

                            cout: out STD_LOGIC;

                            b: in STD_LOGIC_VECTOR (3 downto 0));

end parallel_4;

architecture adder of parallel_4 is

signal c1,c2,c3: std_logic;

component fa

              port(p,q,c: in std_logic;

              s, carry: out std_logic);

end component;

begin

fa1: fa port map (a(0), b(0),cin, sum(0), c1);

fa2: fa port map (a(1), b(1),c1, sum(1), c2);

fa3: fa port map (a(2), b(2),c2, sum(2), c3);

fa4: fa port map (a(3), b(3),c3, sum(3), cout);

end adder;

 

 

 

 

 

 

 

 

SIMULATION RESULTS:

 

6. A VHDL PROGRAM FOR HALF SUBTRACTOR IN STRUCTURAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity hs is

              port (              x: in STD_LOGIC;

                            y: in STD_LOGIC;

                            diff: out STD_LOGIC;

                            borrow: out STD_LOGIC);

end hs;

architecture subtract of hs is

component xor1

              port(a,b: in std_logic;

              c:out std_logic);

end component;

component not1

              port(p: in std_logic;

              z: out std_logic);

end component;

component and1

              port( l,m: in std_logic;

              n:out std_logic);

end component;

signal xbar : std_logic;

begin

d1: xor1 port map (x,y,diff);

n1: not1 port map (x,xbar);

a1: and1 port map (xbar,y,borrow);

end subtract;

SIMULATION RESULTS:

 

7. A VHDL PROGRAM FOR FULL SUBTRACTOR IN DATAFLOW MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity fs is

              port ( x: in STD_LOGIC;

                            y: in STD_LOGIC;

                            bin: in STD_LOGIC;

                            diff: out STD_LOGIC;

                            borrow: out STD_LOGIC);

end fs;

architecture arch of fs is

begin

  diff <= ((not x) and (y xor bin)) or (x and(y xnor bin));

  borrow <= ((not x) and (bin or y)) or (y and bin);

end arch;

 

SIMULATION RESULTS:

 

8. A VHDL PROGRAM FOR 2x4 DECODER IN STRUCTURAL MODEL

Library ieee;

Use ieee.std_logic_1164.all;

entity \2_4decoder\ is

              port(a,b,en :in std_logic;

              d: out std_logic_vector(3 downto 0));             

end \2_4decoder\;

architecture \2_4decoder\ of \2_4decoder\ is

component and_3

              port(x1,x2,x3: in std_logic;

              z1: out std_logic);

end component;

component not1

              port (p: in std_logic;

              z: out std_logic);

end component;

signal a_bar,b_bar: std_logic;

begin             

l1: not1 port map(a,a_bar);

l2: not1 port map(b,b_bar);

l3: and_3 port map(a_bar,b_bar,en,d(0));

l4: and_3 port map(a_bar,b,en,d(1));

l5: and_3 port map(a,b_bar,en,d(2));

l6: and_3 port map(a,b,en,d(3));

end \2_4decoder\;

 

 

 

 

 

SIMULATION RESULTS:

 

9. A VHDL PROGRAM FOR 8 x 3 ENCODER IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity encode8_3 is

              port (              en: in STD_LOGIC;

                            A: in STD_LOGIC_VECTOR (7 downto 0);

                            q: out STD_LOGIC_VECTOR (2 downto 0));

end encode8_3;

architecture arch of encode8_3 is

signal z: std_logic_vector(2 downto 0);

begin

              process(a,en)

              begin

  case A is

                 when "00000001" => z <= "000";

                 when "00000010" => z <= "001";

                 when "00000100" => z <= "010";

                 when "00001000" => z <= "011";

                 when "00010000" => z <= "100";

                 when "00100000" => z <= "101";

                 when "01000000" => z <= "110";

                 when "10000000" => z <= "111";

                 when others => z <= "UUU";

  end case;

  end process;

  q<= z when en = '0' else unaffected;

end arch;

 

 

 

 

SIMULATION RESULTS:

 

10. A VHDL PROGRAM FOR 8 x 3 PRIORITY ENCODER IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

Use ieee.std_logic_arith.all;

entity priorityencoder is

              port (    i: in STD_LOGIC_VECTOR (7 downto 0);

                            en_l: in STD_LOGIC;

                            q: out STD_LOGIC_VECTOR (2 downto 0);

                            gs: out STD_LOGIC);

end priorityencoder;

architecture beh of priorityencoder is

begin

process(i,en_l)

variable j: integer range 7 downto 0;

begin

              if en_l = '1' then gs <='0';

                            q <= "000";

              else

                            for j in 7 downto 0 loop

                                          if i(j) = '1' then gs <= '1';

                                                        q <= conv_std_logic_vector(j,3);

                                                        exit;

                                          else gs <= '0';

                                                        q <= "000";

                                          end if;

                            end loop;

              end if;

              end process;

end beh;

 

SIMULATION RESULTS:

 

11. A VHDL PROGRAM FOR 8 x 3 PRIORITY ENCODER IN DATAFLOW MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity priority is

              port (              i: in STD_LOGIC_VECTOR (7 downto 0);

                            en: in STD_LOGIC;

                            q: out STD_LOGIC_VECTOR (2 downto 0));

end priority;

architecture encoder8_3 of priority is

signal q_i : std_logic_vector(2 downto 0);

signal h: std_logic_vector (7 downto 0);

begin

q <= q_i when en = '1' else "UUU";

              h(7) <= i(7);

              h(6) <= (not i(7)) and i(6);

              h(5) <= (not i(7)) and (not i(6)) and i(5);

              h(4) <= (not i(7)) and (not i(6)) and (not i(5)) and i(4);

              h(3) <= (not i(7)) and (not i(6)) and (not i(5)) and (not i(4)) and i(3);

              h(2) <= (not i(7)) and (not i(6)) and (not i(5)) and (not i(4)) and (not i(3)) and i(2);

              h(1) <= (not i(7)) and (not i(6)) and (not i(5)) and (not i(4)) and (not i(3)) and (not    i(2)) and i(1);

              h(0) <= (not i(7)) and (not i(6)) and (not i(5)) and (not i(4)) and (not i(3)) and (not i(2)) and (not i(1)) and i(0);

              q_i(2) <= h(7)or h(6)or h(5)or h(4);

              q_i(1) <= h(7)or h(6)or h(3)or h(2);

              q_i(0) <= h(7)or h(5)or h(3)or h(1);

end encoder8_3;

 

 

 

 

SIMULATION RESULTS:

 

12. A VHDL PROGRAM FOR 4 x 1 MULTIPLEXER IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity mux4_1 is

              port (              s: in STD_LOGIC_VECTOR (1 downto 0);

                            d: in STD_LOGIC_VECTOR (3 downto 0);

                            y: out STD_LOGIC);

end mux4_1;

architecture beh of mux4_1 is

begin

process(s,d)

begin

              case s is

                            when "00" =>y<= d(0);

                            when "01" =>y<= d(1);

                            when "10" =>y<= d(2);

                            when "11" =>y<= d(3);

                            when others => y <= 'U';

              end case;

end process;

end beh;

 

SIMULATION RESULTS:

13. A VHDL PROGRAM FOR 4 x 1 MULTIPLEXER IN DATAFLOW MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity multiplexer4_1 is

              port(s: in std_logic_vector(1 downto 0);

              d: in std_logic_vector(3 downto 0);

              en: in std_logic;

              y: out std_logic);

end multiplexer4_1;

architecture multiplexer4_1 of multiplexer4_1 is

signal y_i: std_logic;

begin

with s select

y_i <= d(0) when "00",

        d(1) when "01",

        d(2) when "10",

        d(3) when "11",

        'U' when others;

y<= y_i when (not en) = '1' else 'U';

end multiplexer4_1;

SIMULATION RESULTS:

 

14. A VHDL PROGRAM FOR 8 x 1 MULTIPLEXER IN STRUCTURAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity mux8_1 is

              port (              d0,d1,d2,d3,d4,d5,d6,d7: in STD_LOGIC;

                            s0,s1,s2,en: in STD_LOGIC;

                            y: out STD_LOGIC);

end mux8_1;

architecture struct of mux8_1 is

component and5

              port( a,b,c,d,e:in std_logic;

              q: out std_logic);

end component;

component not1

              port( p: in std_logic;

              z: out std_logic);

end component;

component or8

              port(i0,i1,i2,i3,i4,i5,i6,i7: in std_logic;

              r:out std_logic);

end component;

signal s2b,s1b,s0b: std_logic;

signal a1,a2,a3,a4,a5,a6,a7,a8: std_logic;

begin

n1: not1 port map (s0,s0b);

n2: not1 port map (s1,s1b);

n3: not1 port map (s2,s2b);

an1: and5 port map( d0,s2b,s1b,s0b,en,a1);

an2: and5 port map( d1,s2b,s1b,s0,en,a2);

an3: and5 port map( d2,s2b,s1,s0b,en,a3);

an4: and5 port map( d3,s2b,s1,s0,en,a4);

an5: and5 port map( d4,s2,s1b,s0b,en,a5);

an6: and5 port map( d5,s2,s1b,s0,en,a6);

an7: and5 port map( d6,s2,s1,s0b,en,a7);

an8: and5 port map( d7,s2,s1,s0,en,a8);

o1: or8 port map(a1,a2,a3,a4,a5,a6,a7,a8,y);

end struct;

 

SIMULATION RESULTS:

15. A VHDL PROGRAM FOR 3 – BIT COMPARATOR IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity bit_3comparator is

              port(a,b: in std_logic_vector(2 downto 0);

              en: in std_logic;

              agrb,alsb,aeqb: out std_logic);

end bit_3comparator;

architecture bit_3comparator of bit_3comparator is

begin

process(a,b,en)

begin

              if en = '1' then agrb <= '0'; alsb <= '0'; aeqb <= '0';

              elsif en = '0' then

                            if a(2) > b(2) then agrb <= '1'; alsb <= '0'; aeqb <= '0';

                            elsif a(2) < b(2) then agrb <= '0'; alsb <= '1'; aeqb <= '0';

                            elsif a(2) = b(2) and a(1) > b(1) then agrb <= '1'; alsb <= '0'; aeqb <= '0';

                            elsif a(2) = b(2) and a(1) < b(1) then agrb <= '0'; alsb <= '1'; aeqb <= '0';

                            elsif a(2) = b(2) and a(1) = b(1) and a(0) > b(0) then agrb <= '1'; alsb <= '0'; aeqb <= '0';

                            elsif a(2) = b(2) and a(1) = b(1) and a(0) < b(0) then agrb <= '0'; alsb <= '1'; aeqb <= '0';

                            else agrb <= '0'; alsb <= '0'; aeqb <= '1';

                            end if;

              end if;

end process;

end bit_3comparator;

 

SIMULATION RESULTS:

 

16. A VHDL PROGRAM FOR 4 – BIT COMPARATOR IN STRUCTURAL MODEL

Library ieee;

Use ieee.std_logic_1164.all;

entity bit_4comparator is

          port(  p, q: in std_logic_vector (3 downto 0);

                      p_notequal_q: out std_logic);

end bit_4comparator;

architecture bit_4comparator of bit_4comparator is

component xor1

              port(a,b: in std_logic;

              c: out std_logic);

end component;

component or4

              port(u,v,w,x: in std_logic;

              o: out std_logic);

end component;

component not1

              port(p: in std_logic;

              z: out std_logic);

end component;

signal diff0,diff1,diff2,diff3: std_logic;

begin

c1: xor1 port map(p(0),q(0),diff0);

c2: xor1 port map(p(1),q(1),diff1);

c3: xor1 port map(p(2),q(2),diff2);

c4: xor1 port map(p(3),q(3),diff3);

c5: or4 port map(diff0,diff1,diff2,diff3,p_notequal_q);

end bit_4comparator;

 

SIMULATION RESULTS:

 

17. A VHDL PROGRAM FOR A 4 – BIT / MOD 16 COUNTER IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

Use IEEE. std_logic_unsigned.all;

entity count_4 is

              port (   clk: in STD_LOGIC;

                            q: out STD_LOGIC_VECTOR (3 downto 0);

                            res: in STD_LOGIC);

end count_4;

architecture arch of count_4 is

signal count: std_logic_vector(3 downto 0):= "0000";

begin

              process (clk, res)

              begin

              if res = '1' then count <= "0000";

              elsif clk'event and clk = '1' and res = '0' then

                            if count = "1111" then count <= "0000";

                            else count <=  count + "0001";

                            end if;

              end if;

              end process;

                            q<= count;

end arch;

 

 

 

SIMULATION RESULTS:

 

18. A VHDL PROGRAM FOR A 4 – BIT UP – DOWN COUNTER IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity upndown is

              port (              clk: in STD_LOGIC;

                            res: in STD_LOGIC;

                            up: in STD_LOGIC;

                            down: in STD_LOGIC;

                            q: out STD_LOGIC_VECTOR (3 downto 0));

end upndown;

architecture count of upndown is

signal count: std_logic_vector(3 downto 0):= "0000";

signal ud: std_logic_vector(1 downto 0);

begin

              ud <= up & down;

              process(clk,count,ud)

              begin

              if clk'event and clk = '1' then

                            if res = '1' then count <= "0000";

                            elsif ud = "10" then count <= count + "0001";

                            elsif ud = "01" then count <= count              - "0001";

                            else count <= count;

                            end if;

              end if;              q <= count;

              end process;                           

end count;

 

 

 

 

SIMULATION RESULTS:

 

19. A VHDL PROGRAM FOR D FLIP – FLOP IN STRUCTURAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity dff is

              port (              d: in STD_LOGIC;

                            clk: in STD_LOGIC;

                            q: in STD_LOGIC;

                            qbar: inout STD_LOGIC;

                            qt: inout STD_LOGIC;

                            qtbar: out STD_LOGIC);

end dff;

architecture arch of dff is

component nand1 port(a,b: in std_logic;

              c:out std_logic);

end component;

component not1

              port(p:in std_logic;

              z:out std_logic);

end component;

signal n1,n2,n3:std_logic;

begin

  n:not1 port map (d,n1);

  nn:not1 port map(q, qbar);

  o1: nand1 port map(d, clk, n2);

  o2: nand1 port map(n1, clk, n3);

  o3: nand1 port map(n2, qbar, qt);

  o4: nand1 port map(n3,qt,qtbar);

end arch;

 

 

 

SIMULATION RESULTS:

 

20. A VHDL PROGRAM FOR A D FLIP – FLOP IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity dff1 is

              port ( d: in STD_LOGIC;

                               clk: in STD_LOGIC;

                               clr: in STD_LOGIC;

                               q: out STD_LOGIC;

                               qn: out STD_LOGIC);

end dff1;

architecture arch of dff1 is

begin

  process (clk, clr)

  begin

                if clr = '1' then q<= '0'; qn <= '1';

                elsif clk'event and clk = '1' then q <= d; qn<= not d;

                end if;

  end process;

end arch;

 

SIMULATION RESULTS:

 

21. A VHDL PROGRAM FOR A S-R FLIP FLOP IN BEHAVIORAL MODEL

Library ieee;

Use ieee.std_logic_1164.all;

entity sr_ff is

              port(s,r,clk,q: in STD_LOGIC;

              qt: out STD_LOGIC);

end sr_ff;

architecture sr_ff of sr_ff is

signal t: std_logic_vector(1 downto 0);

begin

  process(s,r,clk)

  begin

                t <= s & r;

                if (clk'event and clk = '1') then

                              if t = "00" then qt <= q;

                              elsif t = "01" then qt <= '0';

                              elsif t = "10" then qt <= '1';

                              elsif t = "11" then qt <= 'U';

                                            else qt <= 'U';

                              end if;

                end if;

  end process;

end sr_ff;

 

SIMULATION RESULTS:

 

22. A PROGRAM FOR J – K FLIP – FLOP IN DATA FLOW MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity jkff is

              port (              j,k,clk,q: in STD_LOGIC;

                            qbar: inout STD_LOGIC;

                            qt: out STD_LOGIC);

end jkff;

architecture arch of jkff is

begin

  qbar <= not q;

  qt <= (j and qbar and clk) or ((not k) and q and clk);

end arch;

SIMULATION RESULTS:

 

23. A PROGRAM FOR A T FLIP – FLOP IN DATA FLOW MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity tff is

              port (              t,q: in STD_LOGIC;

                            clk: in STD_LOGIC;

                            qn: out STD_LOGIC);

end tff;

architecture arch of tff is

begin

  qn <= (t xor q) and clk;

end arch;

SIMULATION RESULTS:

 

24. A PROGRAM FOR A COMBINATIONAL MULTIPLIER IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity multiplier is

              port (              x: in STD_LOGIC_VECTOR (3 downto 0);

                            y: in STD_LOGIC_VECTOR (3 downto 0);

                            p: out STD_LOGIC_VECTOR (7 downto 0));

end multiplier;

architecture arch of multiplier is

function carry (i1,i2,i3: std_logic) return std_logic is

begin

              return ((i1 and i2) or (i1 and i3) or (i2 and i3));

end carry;

begin

              process( x,y )

type array4_4 is array (0 to 3) of std_logic_vector( 3 downto 0);

variable pc,pcs,pcc: array4_4;

variable ras,rac: std_logic_vector (3 downto 0);

begin

              for i in 0 to 3 loop

                            for j in 0 to 3 loop

                                          pc(i)(j) := y(i) and x(j);

                            end loop;

              end loop;

              for j in 0 to 3 loop

                            pcs(0)(j) := pc(0)(j);

                            pcc(0)(j) := '0';

              end loop;

              for i in 1 to 3 loop

                            for j in 0 to 2 loop

                                          pcs(i)(j) := pc(i)(j) xor pcs(i-1)(j+1) xor pcc(i-1)(j);

                                          pcc(i)(j) := carry(pc(i)(j), pcs(i-1)(j+1), pcc(i-1)(j));

                                          pcs(i)(3) := pc(i)(3);

                            end loop;

              end loop;

              rac(0) := '0';

              for i in 0 to 2 loop

                            ras(i) := pcs(3)(i+1) xor pcc(3)(i) xor rac(i);

                            rac(i+1) := carry (pcs(3)(i+1), pcc(3)(i), rac(i));

              end loop;

              for i in 0 to 3 loop

                            p(i) <= pcs(i)(0);

              end loop;

              for i in 4 to 6 loop

                            p(i) <= ras(i-4);

              end loop;

              p(7) <= rac(3);

end process;

end arch;

 

 

 

 

SIMULATION RESULTS:

 

25. A PROGRAM FOR ARITHMETIC LOGIC UNIT (ALU) IN BEHAVIORAL MODEL

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee.std_logic_unsigned.all;

entity alu1 is

port(a,b:in std_logic_vector(3 downto 0);

     c1:out std_logic_vector(7 downto 0);

     op:in std_logic_vector(2 downto 0));

end alu1;

architecture alu1 of alu1 is

begin

  process(a,b,op)

  begin

                c1 <="00000000";

  case op is

  when "001"=>c1<=a+b;

  when "010"=>c1<=a-b;

  when "011"=>c1<=a*b;

  when "100"=>c1<=a and b;

  when "101"=>c1<=a or b;

  when "110"=>c1<=not(a);

  when "111"=>c1<=a xor b;

  when others=>c1<="00000000";

  end case;

  end process;

end alu1;

 

 

 

SIMULATION RESULTS:

 

26. A PROGRAM FOR SHIFTING 8-BIT DATA LEFT BY 2 BITS IN BEHAVIORAL MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

entity leftshifter is

              port(din: in STD_LOGIC_VECTOR(7 downto 0);

              dout: out STD_LOGIC_VECTOR(7 downto 0));

end leftshifter;

architecture leftshifter of leftshifter is

begin

  process(din)

  variable i : integer;

  begin

              a: for i in 0 to 5 loop

                            dout(i+2) <= din(i);

                end loop;

                dout(0) <= '0';

                dout(1) <= '0';

  end process;

end leftshifter;

 

SIMULATION RESULTS:

 

27. A VHDL PROGRAM TO FIND 2’S COMPLEMENT OF 8 – BIT DATA IN DATAFLOW MODEL

Library IEEE;

Use IEEE.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity compl_2 is

              port ( din: in STD_LOGIC_VECTOR(7 downto 0);

                               dout: out STD_LOGIC_VECTOR(7 downto 0));

end compl_2;

architecture compl_2 of compl_2 is

signal compl_1: std_logic_vector(7 downto 0);

begin

              compl_1 <= not(din);

              dout <= compl_1 +'1';

end compl_2;

 

 

 

 

 

 

SIMULATION RESULTS:

 

28. A PROGRAM FOR A FSM TO DETECT THE SEQUENCES “1011”, “1010”, “1000” IN BEHAVIORAL MODEL

Library ieee;

Use ieee.std_logic_1164.all;

entity fsm is port(x, clk: in STD_LOGIC;

              Z: out STD_LOGIC);

end fsm;

architecture design of fsm is 

subtype state_type is std_logic_vector(2 downto 0) ;

signal state, next_state: state_type;

constant A:state_type :="000";

constant B:state_type :="001";

constant C:state_type :="010";

constant D:state_type :="011";

constant E:state_type :="100";

constant F:state_type :="101";

begin

              process(clk)

              begin

                            if clk'event and clk = '1' then

                                          state <= next_state ;

                            end if;

              end process;

              process(x, state)

              begin

                            case state is

                                          when A => if x = '0' then next_state <= A; Z <= '0';

                                          elsif x = '1' then next_state <= B; Z <= '0';

                                          end if;             

                                          when B => if x = '0' then next_state <= C; Z <= '0';

                                          elsif x = '1' then next_state <= B; Z <= '0';

                                          end if;

                                          when C => if x = '0' then next_state <= F; Z <= '0';

                                          elsif x = '1' then next_state <= D; Z <= '0';

                                          end if;

                                          when D => if x = '0' then next_state <= C; Z <= '1';

                                          elsif x = '1' then next_state <= E; Z <= '1';

                                          end if;

                                          when E => if x = '0' then next_state <= C; Z <= '0';

                                          elsif x = '1' then next_state <= A; Z <= '0';

                                          end if;

                                        when F => if x = '0' then next_state <= A; Z <= '1';

                                          elsif x = '1' then next_state <= B; Z <= '0';

                                          end if;

                                          when others => next_state <= A;

                            end case;

              end process;

end design;

 

 

SIMULATION RESULTS:

Detecting “1000” sequence:

 

Detecting “1011” sequence:

48

 


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