RSRTC Recruitment 2011 Admit CardThe written exam tentative date is 18/12/2011 instead of 27/11/2011.For more detail please see here:
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|Last Updation: 16/11/2011|
Details of Part Time Programs of JNTU- H:
1. M.Tech: Specialisations in Civil / Mechanical/ Biotechnology/ EEE / Energy Systems/ Environmental Management/ Computer Science/ Remote Sensing and GIS/System and Signal Processing/ Water and Environmental Technology/ Metallurgical Engineering.
2. M.Pharmacy: Pharmaceutical Biotechnology
3. M.Sc.: Applied Chemistry / Physics
4. M.B.A.: HR/ Finance/ Marketing/ Systems
Essential Eligibility for all the programs: Candidates shold be employed on regular basis in Hyderabad or it's surrounding areas. They should have work experience of at least one year by 30th June 2011. Apart from this they should have prescribed educational qualifications for all the programs. These details are available on www.jntuh.ac.in.
Application Procedure: Candidates can obtain application format from JNTUH website mentioned above. Test Syllabus for written exam, Eligibility Criteria and other details also available on website. Application fee is Rs. 1000. Address: Jawaharlal Nehru Technological University, Kukatpally, Hyderabad - 500085, Andhra Pradesh, India. Phones : +91-040-23158661 to 23158664.
1. Last date for submission of applications: 25-04-2011
2. Entrance Examination Dates: 14th, 15th and 16th May 2011.
Osmania University B.Ed 3rd Methodology Admissions 2012
Interested candidates can obtain application forms from the Director, CBMDM, IASE, Osmania University in person or through post on payment of Rs. 300 as application fee. Application cost through post is Rs. 330. Fee should be paid in the form of DD drawn in favour of Director, CBMDM, IASE, OU, Hyderabad and payable at Hyderabad. More details can be obtained from www.osmania.ac.in
1) Commencement of sale of applications: 15-11-2011
2) Last date for the sale of applications: 14-12-2011
3) Last date for the submission of completed applications: 17-12-2011
Verilog is a one of the famous Hardware Descriptive Languages (HDL). (VHDL is the other one). Verilog langauage syntax very well matches with C language syntax. This is big advantage in learning Verilog. Logic operators, data types, loops are similar to C. In addition to this certain data types which are necessary to describe a hardware are available in Verilog. For example, nets in a schematic or hardware design is refered here as 'wire'. Flip-flops (or in general are called as registers) are defined as type 'reg'.
"module"s are building block of Verilog. Consider any design represented by a block diagram with its inputs and outputs.
input ---- ; // telll which are inputs
output ---- ; //these are outputs
module ==> Verilog keyword to declare a name of the hardware circuit.
==> Name of the module i.e. hardware circuit. (Here it is "A").
==> 'terminal' is Verilog way of naming I/O ports, here we should specify all inputs and outputs of circuit. Outputs are written first. Why? Answer is "That's how Verilog is !!!!"
input ==> Verilog keyword to tell the Verilog compiler which are inputs of the module in the given list of .
output ==> Verilog keyword to tell the Verilog compiler which are outputs of the module in the given list of .
endmodule ==> Another verilog keyword to tell that module related all definitions are over and this is the end of the module.
; ==> This semi colon represents end of line.
// --> represents start of comment; same as C syntax.
( /*……………………………..*/ are multiple line comment)
So above design "A" can be defined in Verilog as given below:
module A (Output1, Input1, Input2)
input Input1, Input2;
If above design is a T flip-flop then we can write module description as:
module T_FF(q,clock,reset); // Here q is o/p; must be first
//Other control i/pts must be next i.e. clk and reset inputs]
Nesting of modules is not allowed in verilog. One module definition can't contain another module definition within the 'module ' and 'endmodule' statements.
Hardware circuit of design "A" can be defined in 3 different ways in Verilog. They are:
1. Gate level modeling
2. Data flow modeling
3. Behavioural modeling
THIS IS FROM comp.arch.fpga group ......
I am an ASIC design engineer with over 6 years experience. My experience
in ASIC design spans across microarchitecture, RTL coding, synthesis,
timing closure and verification. Is it advisable for me if I change to a
FPGA design job? I mean, what are the pros and cons? I do not have much
experience in FPGA other than school projects. How much learning is
involved? Will it be difficult to switch back to ASIC design position in
the future if I move to a FPGA job? Do FPGA design involve less work and
stress than ASIC? Please provide your opinion, experience or any other
years had yearned to do ASIC design with the "big boys". He lasted a
year or two -- not because he wasn't up to the job, but because he hadn't
realized the difference in the design cycle between ASIC and FPGA, and he
vastly preferred FPGA design.
Because with FPGA design, you do your system design and have a design
review, then you do your coding and have a design review, and then you
pour it all into the PC board that's been underway at the same time that
you were doing your FPGA design. You bring it all up with the test
features in the software whose design has _also_ been underway while you
were working, and you test the heck out of it.
At this point, you're far from done: the board will be getting green
wires, the software will be getting revised (or, if everyone is smart,
only the critical portions of the software will have been completed), and
your logic design will probably need revision (or be incomplete).
So it's not uncommon to spend a month or two tweaking and revising your
"finished" design after it's finished.
Tom's experience with ASIC design, on the other hand, was that you get
the system design done, then you go write a bunch of behavioral code to
completely embody the system design, and a testbench to completely test
it. You churn on that for weeks or months while your colleagues make up
new tests for corner cases.
Then, once you've verified the snot out of the system design, you start
replacing parts of your behavioral system piece-by-piece with the RTL-
level code for your ASIC, testing all the way.
So, (in Tom's words), you spend 90% of your time flogging the
This all makes sense: the cycle time between moving a comma in a Verilog
file and testing the effect in an FPGA might only take between half an
hour and several hours. The cycle time to do the same thing with an ASIC
is weeks, and $$$, and trash bins full of parts. So doing the
verification "live" makes good economic sense with FPGAs, and doing it in
simulation makes equally good economic sense with ASICs.
So: if the design cycle that I'm quoting for ASICs sounds accurate to
you (I'm just forwarding a long-ago conversation), and the design cycle
for FPGA work makes you think "ewww!", then FPGA work isn't for you. If,
on the other hand, you get no joy from spending 90% of your time
verifying before you actually get to see your work working -- maybe
you'll like FPGA work.
Tom did note barriers to transitioning to ASIC work (in part because he
has an EET degree, not a "real" EE degree), and may not have found the
transition back to FPGA work as easy as he did if he did not have a large
circle of former coworkers who -- to a man -- were impressed by his work
and willing to tell their bosses. (Tom's one of those guys that if he's
applying for work you tell your boss "just hire him, he'll make it work").
So, that's what I know.