UPSC CPF Assistant Commandant (AC) Exam 2011 Answer Key

UPSC CPF Assistant Commandant (AC) Exam 2011 Answer Key / Cut Off

 The CPF Assistant Commandant Exam Was Held At 08 Oct 2011. Candidates Can Discuss Here For Estimated Cut Off Of Assistant Commandant Exam.
answers  :

1. mangala s in rajasthan.

2. govind dev ji temple jaipur.

3. industrial minister rajendra pareek.

4. jo rajasthan ka CM Kabhi nahi rahe.
shivraj patil

5. present CM jodhpur se jeete the election.

6. president nd raj ki personality pratibha devi singh.

7. rajasthan ka border pakistan se.

8. rajasthan ka border jis se nahi lagta uttarakhand.

9. bankers of d bank rbi.

10. jo ek financial institution nahi h UNESCO.

11. cAttle fair
pushkar n jalore dono me hota h.

12. foreign secretary ranjan mathai.

13. haldi ghati maharana pratap nd akbar.

14. electrification to villages of bpl kutir jyoti.

15. iit ki coaching kota.

16. rajasthan mein hawa mahal.

17. pakistan ki foreign minister hina rabbani khan.

18. census 2011 raj ki literacy rate 68.

19. Pm kaha gaye the china…?

20. sports personality gagan narang.

21. defence personnel ko kirti chakra.

22. sports me arjuna award.

23. ranji tropy cricket.

24. raj se loksabha me 25 seats.

25. gas nahi h cobalt.

26. CAG ki full form.
comptroller nd general auditor.

27. india ki space agency ISRO.

28. raj me coconut k ped nahi hote.

29. IGNP jaisalmer par end hoti h.

30. raj k west mein thar desert.

31. agriculture crop nahi h alum/ fitkari.

32. raj me chambal nadi.

33. nuclear plant rawatbhata.

34. raj mai konsa elemnt nai milta?

35.dalal street bombay stock xchange.

36. district nahi h raj ki.

37. wto me t s trade.

38. hamid ansari
s vice president.

39. world economic forum May 2011 ka kaha hua tha.



1. we have deny tha.
denied hoga

2. will be promoting tha.
error h
passive voice verb ki third form again.

3. he asked me k baad that nd if ka use ek sath tha.

4. uska frd motivator.

5. only c

6. wants to participate in olympic.

7. mastering acquiring d skill.

8. heal% recover



1.    ravi nd vinay age ques ka ans 16.

2.    men women children ka 48 days.

3.    simple interest 3315.

4.     perimeter 126m

5.    substract to bcome dat no square 14.

6.    37 ka squre.

ka share 16000.

7.    150 k teen parts second no 50.

A friend omiomi says here that he/she got set D.. he have checked answers of almost 90 questions. he typed answers according to questions so check accordinly ...
1.border forces match the following- c
2.mountain ranges fron north to south match- a
3.golden chariot- a(hyderbad)
4.lokhpal bill commetee 2011- d
5.festival-ethenic match- a
6.regional rural bank - d
7.10000 mw hydropower - a(bhutan)
8.federal used- d(nowhere)
9.vechicles-mettalic ropes-d
10.poluted surface water sequence- c
11.father mother bloood group-c
12.shape of population-c
13.retreatin monsoon-d
14.econmy owed factor of production-d(both socialist and capitalist)
15.heat transmitted from sun to earth-c(radiation)
16. cyclone related-c
17.wind velocity-d(pressure gradient)
18.planet venus-c
19.river match-a
21.prominent american match-a
23-treaty of madras-c
24.painter mughal-d(baz bahadur)
26.jamnalal match-d
27.indian freedom match-c
28-malabar-07-2- a
29. j-10 fighter- c
31.right to informat- b
32.emergency loksabha- c
33.rajya sabha-d
34fundamental duites-c
35.heavy water-d
36.first nuclear reactor-d
37. ratio of boys and girls... in a sequence(its same for everyone)
38.elderly person 25 cm-c
39. everyone has father-c
41.nato-d(afganishthan) bring together-d( aman ki asha)
43.plantation crop-c(wheat)
44.demograpgic transition-c
45. population density-b
46.diagram of circles traingles(in sequence)
47.rural settlement- a(primary)
48.ongc- d(imperial energy)
50- kankesanthurai-b
51.prahar missle-c

rest he have little doubt so he didnt upload.

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Steve Jobs, 1955 – 2011

Verilog vs VHDL:Salient Features of Languages

Salient Features of Languages


Some of the most widely compared and contrasted features of Verilog and VHDL are:


1.  Concurrency : A common characteristic of both these hardware description languages is that unlike software programming languages like C, Java and C++ etc., both these languages are concurrent in their behavior and program execution, as these languages are meant to design and simulate hardware.

2.     Predefined Constructs: As compared with VHDL, Verilog HDL has more predefined operators, predefined gates and predefined resolution functions. Verilog also includes don't care notation.

3.      Lower Level Modeling Capability: Verilog is better suited to modeling devices at lower level (i.e., Gate Level and Switch Level) than VHDL. This is why Verilog is deemed more efficient and appropriate for IC designing.

4.      Modeling Primitive Capability: As compared with VHDL, Verilog includes convenient truth table syntax to model primitives. However, the VITAL packages in VHDL provide this feature.

5.      High Level Modeling Capability: As compared with Verilog, VHDL includes more constructs (abstract data types and packages etc.) for high level modeling. This is why VHDL is considered appropriate for system level modeling.

6.      Case Sensitivity: Unlike VHDL, Verilog is a case sensitive language.

7.      Semantics: Both VHDL and Verilog have simulation-based semantics.

8.      Compilation and Interpretation: VHDL is compiled, while Verilog is an interpretative language.

9.      Simulation and Control Capabilities: Verilog defines a set of basic simulation control capabilities (system tasks) within language. As a result of these predefined system tasks and a lack of complex data types, Verilog users often run batch or command-line simulations and debug design problems by viewing waveforms from simulation results database. Unlike Verilog, VHDL does not define any simulation control and monitoring capabilities within language. These capabilities are tool-dependent. Due to the lack of language-defined simulation control command and because of user defined type capabilities, VHDL users usually rely on interactive GUI environments for debugging design problems.

10.  Dynamic Memory Allocation: VHDL supports dynamic memory allocation (pointer types), while Verilog has no such feature.

11.  Roots of Languages: VHDL is more readable and a strongly typed language with its roots from Ada. While, Verilog because of having its roots from C is more like C and is considered inherently sequential. Because of its affinity with C, Verilog is preferred by C programmers.

12.  Lack of Constructs: Not all the constructs and operators are included in both languages. For example, unlike Verilog, VHDL does not have unary reduction operator. Similarly, unlike VHDL, Verilog does not have mod operator and concurrent procedure statement. So neither of these two hardware description languages is perfect.

13.  Data types: Verilog has very simple data types, while VHDL allows users to create more complex data types.  

14.  Physical Types: VHDL supports physical types while Verilog does not support physical types.

15.  Named Events: Verilog supports named events while VHDL does not support named events.

16.  Enumerated Types: VHDLhas enumerated types (FSM modeling) while Verilog does not support this concept.  

17. Associative/Sparse arrays: Verilog does not support the concept of Associative/sparse arrays,while VHDL partially supports this concept,which can be modeled in VHDL using access types.

18. Associative/Sparse arrays: There is no concept of class/inheritance in both Verilog and VHDL. 

19. Data Packing: Both Verilog and VHDL do not support data packing.  

20. Conidtional & Iterative Generation: Both Verilog (using if,if-else,case and for) and VHDL (using if and for) support conditional and iterative genration.   


Verilog vs VHDL:Superior Features of Verilog

Superior Features of  Verilog:

·         Verilog has clearer distinction between register and nets. Nets are used to model electrical connections, while registers hold values and act as memory elements.

·         Nets have strengths and delay properties which emphasize their physical aspects. The delay may consist of up to 9 values; a different value may be assigned for each transition 0, 1 or z and for each minimum, typical and maximum case. Such a delay attached to a net is added to the delay of each assigned statement. The net types include wire,tri,wand,triand,wor,trior,tri0,tril(resistive),supply0,supply1 and trireg (with charge storage).

·         Primitive gates include and, or, xor & not.

·         Verilog is concise and easier to learn as compared with VHDL. Unlike Verilog, VHDL is extremely verbose, which means it requires many characters to say something simple. This is why there are many different ways of saying the same thing in VHDL which makes it complicated and confusing. VHDL is exact in nature and difficult to learn. Verilog is deemed quicker to code and debug as compared with VHDL.

·         Unlike VHDL, Verilog has fork-join block. This construct lets you have nested parallel sequential blocks inside each other. This is a very powerful feature which is sometimes termed as 'multi-threading'. You cannot have this feature in VHDL unless you use explicit synchronizations between two different processes.

·         Unlike VHDL, Verilog is not a strongly typed language and this is why a 32-bit bus may be connected with and 8-bit bus by just padding the extra bits. Verilog does not require additional coding to convert from one data type to another data type like integer to bit-vector. So it does not have to pay the performance penalty caused by strong type checking and the designer productivity is also expected to be high in this case.

Verilog vs VHDL :Superior Features of VHDL

 Superior Features of  VHDL:

·        Unlike Verilog, the concept of packages in VHDL, library management and separate compilation makes it an ideal candidate for higher level system modeling. There is no concept of packages in Verilog. Functions and procedures used within a module have to be defined inside the same module and thus they cannot be shared by different modules. However, the concept of package in Verilog may be emulated by declaring and instantiating a fictitious module with functions and procedures. Verilog, unlike VHDL, does not support library management and separate compilation. This is why; Verilog requires all modules being used in same simulation must be written in the same file.

·         Unlike VHDL, Verilog types are very restrictive and are specific to IC modeling (wire, supply0, supply1 etc.). Many abstract data types may be defined in VHDL while Verilog data types are predefined.

·         Unlike VHDL, Verilog has no concept of configurations and it lacks generics and textio.

·         Unlike VHDL, Verilog has no access types.

·         Unlike Verilog, VHDL has extensive type checking feature; this is why many errors may be caught before synthesis and simulation.

·         VHDL provides more details in assignment and application of individual cells and signals within FPGA, but this requires a much better understanding of the FPGA. As compared with VHDL, Verilog despite being much easier to learn is neither efficient in use of available cells nor does it necessarily generate the fastest running implementation from the components available in FPGA.

·         Unlike Verilog, the verbosity of VHDL makes it self-documenting.

·         VHDL semantics are unambiguous and VHDL based design may easily be ported from one tool to another. This is why race conditions are never a concern for VHDL users. Simulation semantics in Verilog are more ambiguous than in VHDL. Though this ambiguity in Verilog semantics, gives designer more flexibility in applying optimization but it can also (and often does) result in race conditions if careful coding guidelines are not followed. It is highly probable that a Verilog based design generates different results on different vendors' tools or on different releases of the same vendor's tool.  

·         The advantage of strong typing in VHDL is that the potential bugs in the design may be identified as early in a verification process as possible. Many problems that strong typing uncover are identified during analysis/compilation of the source code.

Verilog vs VHDL



Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different origins. Both of these languages hold major market shares of hardware description languages being used around the globe. It is difficult to say with certainty which one is better or superior; however, VHDL is older of the two. You can produce robust designs and comprehensive test environments with both languages, for both ASIC and FPGA.  


History and Origin of Languages


Both Verilog and VHDL have originated from different programming languages and are supported by different schools of thought. VHDL is based on Pascal and Ada, thus characteristics of both of these languages are reflected by VHDL. Verilog, unlike VHDL, is based on C programming language and is relatively new as compared with VHDL. Internet sources claim that Verilog is supported mostly by the HDL programmers with industrial experience and background while VHDL is supported mostly by academic circles.

The development of VHDL was initiated in 1981 by United States Department of Defense (DOD) to address the hardware life cycle crisis. VHDL was developed for US Department of Defense (DOD) to provide a consistent hardware modeling language for documentation of digital hardware designs. It was never meant to design actual hardware; its sole purpose was hardware modeling. Since Verilog HDL was an intellectual property of Gateway Design Automation, which was eventually acquired by Cadence, so to maintain the supposed competitive advantage and distance themselves from any strategic ties to Verilog HDL to avoid any potential competitive control from Cadence, the individual Electronic Design Automation (EDA) companies extended considerable influence, resources and dollars to turn this language into a hardware design language. These same individual EDA companies developed and implemented their own semi-unique versions of the language at different stages of its development and implementation. The reason that these EDA companies did not adopt Verilog HDL is that they all have a basic philosophy which states that they must own all of their core technology which was being violated in case of Verilog as it, being intellectual property of Cadence, was not open to public domain. Besides this the EDA vendors wanted to break Cadence's stranglehold on the software design tool and IC design market by pushing and promoting VHDL, which was an open language. VHDL became IEEE standard 1076 in 1987.VHDL was updated in 1993 and is known today as "IEEE standard 1076 1993".As an IEEE standard, VHDL must undergo a review process every five years or sooner to ensure its ongoing relevance to industry. The first such revision was completed in September 1993.

Unlike VHDL, Verilog has originated from the commercial and industrial world. It was developed as a part of a complete simulation system, which may be utilized for describing digital hardware systems as well. Verilog HDL was launched by Gateway in 1983.Gateway was bought by Cadence in 1989.Cadence had recognized that if Verilog HDL remained a closed language as compared with VHDL the pressures of standardizations would force the industry to VHDL. So Cadence opened Verilog to the public domain in 1991 by officially publishing it. Verilog HDL became IEEE standard in 1995.


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