List of Verilog Simulators in Alphabetical Order by Name

Simulator Name Author/Company Languages Description
List of Verilog Simulators in Alphabetical Order by Name
Active-HDL/Riviera Aldec VHDL-2002, V2001, SV2005 A simulator with complete design environment aimed at FPGA-applications. Aldec licenses Active-HDL to FPGA-vendors, and the underlying engine can be found in the design-suites of those vendors. While ActiveHDL is a low-cost product, Aldec also offers a more expensive, higher-performance simulator called "Riviera."
Quartus II Simulator Altera VHDL-1993, V2001, SV2005 Altera's simulator bundled with the Quartus II design software. Supports Verilog, VHDL and AHDL.
Verilog-XL Cadence V1995 The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. Cadence recommends Incisive Enterprise Simulator for new design projects, as XL no longer receives active development. Nevertheless, XL continues to find use in companies with large codebases of legacy Verilog. Many early Verilog codebases will only simulate properly in Verilog-XL, due to variation in language implementation of other simulators.
Speedsim Cadence Design Systems V1995 Cycle based simulator originally developed at DEC. The DEC developers spun off to form Quickturn Design Systems. Quickturn was later acquired by Cadence, who discontinued the product in 2005. Speedsim featured an innovative slotted bit-slice architecture that supported simulation of up to 32 tests in parallel.
Incisive Enterprise Simulator('big 3') Cadence Design Systems VHDL-2002, V2001, SV2005 Cadence initially acquired Gateway Design, thereby acquiring Verilog-XL. In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. The modern version of the NCsim family, called Incisive Enterprise Simulator, includes Verilog, VHDL, and SystemVerilog support. It also provides support for the e verification language, and a fast SystemC simulation kernel.
SMASH Dolphin Integration V1995, V2001, VHDL-1993 SMASH is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms.
Super-FinSim Fintronic V2001 This simulator is available on multi-platform, claiming IEEE 1364-2001 compliance.
PureSpeed Frontline V1995 The simulator had a cycle-based counterpart called 'pure cycle'. FrontLine was sold to Avant!, which was later acquired by Synopsys. Synopsys discontinued Purespeed in favor of its well-established VCS simulator.
ModelSim('big 3') Mentor Graphics VHDL-2002, V2001, SV2005 The original Modeltech (VHDL) simulator was the first mixed-language simulator capable of simulating VHDL and Verilog design entities together. However, as the Verilog component of ModelSim is neither the fastest nor most fully featured simulator on the market, competition from Synopsys and Cadence, led to a continual decrease in ModelSim popularity.
SILOS Simucad Design Automation V2001 As one of the low-cost interpreted Verilog simulators, Silos III enjoyed great popularity in the 1990s. Simucad's most current version, Silos-X, is sold as part of a tool-suite.
Veritak Sugawara Systems V2001 It is low-cost and Windows-based only. It boasts a built-in waveform viewer and fast execution.
Verilogger Extreme,Verilogger Pro SynaptiCAD V2001,V1995 Verilogger Pro is a low-cost interpreted simulator based on Elliot Mednick's VeriWell code base. Verilogger Extreme is a newer, compiled-code simulator that is Verilog-2001 compliant and much faster than Pro.
VCS Synopsys VHDL-2002, V2001, SV2005 Originally developed by John Sanguinetti, Peter Eichenberger and Michael McNamara under the startup company Chronologic Simulation, VCS (Verilog Compiled code Simulator) was purchased by Synopsys, where development continued. Due to a strategic decision to support SystemVerilog (instead of SystemC), and the acquisition of Superlog (the forerunner to SystemVerilog), Synopsys/VCS was the first SystemVerilog simulator in the market.
CVC Tachyon Design Automation V2001, V2005 CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode.
Z01X WinterLogic V2001,SV2005 Developed as a fault simulator but can also be used as a logic simulator.
ISE Simulator Xilinx VHDL-93, V2001 Xilinx's simulator comes bundled with the ISE Design Suite. ISE Simulator (ISim) provides support for mixed-mode language simulation including, but not limited to, simulation of designs targeted for Xilinx's FPGAs and CPLDs.

Some commercial simulators (such as ModelSim) are available in student, or evaluation/demo editions. These editions generally have many features disabled, arbitrary limits on simulation design size, but are offered free of charge.

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The world's highest webcam was installed on Kala Patthar, a smaller
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18618 feet (5675 metres). The webcam can withstand temperature as low
as minus 30 degrees Celsius and operates from 6 a.m. to 6 p.m. The Web
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The German surveillance firm Mobotix developed the device and it was
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Caching in


Introduction: It is a way to store the frequently used data into the server memory which can be retrieved very quickly. And so provides both scalability and performance. For example if user is required to fetch the same data from database frequently then the resultant data can be stored into the server memory and later retrieved in very less time (better performance). And the same time the application can serve more page request in the same time (scalability).

Drawback: Suppose the server memory is filled with the data then the remaining part of the data is stored into the disk which slower the complete system performance. That's why self limiting caching techniques are best; where once the server memory gets filled the data has been selectively removed from the server memory to ensure that the application performance is not degraded.

Caching Types: Basically, caching is of two types:

  1. Output caching - The rendered html page is stored into the cache before sending it to the client. Now, if the same page is requested by some other client the already rendered htm page is retrieved from the server memory and sent to the client, which saves the time requires rendering and processing the complete page.
  2. Data Caching - The important pieces of information, that are time consuming and frequently requested, are stored into the cache. For example a data set retrieved from the database. It is very similar to application state but it is more server friendly as the data gets removed once the cache is filled.

There are two more models which are built on the above two types: 

  1. Fragment caching - Instead of caching the complete page, some portion of the rendered html page is cached. E.g.: User Control used into the page is cached and so it doesn't get loaded every time the page is rendered. 
  2. Data Source Caching - It is caching built into the data source controls (eg. XmlDataSource, sqlDataSource etc). It is very similar to data caching but here the caching is not handled explicitly but the data source control manages it as per the settings made on the data controls.